1. Field of the Invention
The present invention relates to an output buffer circuit for an LSI including bipolar transistors and CMOSs.
2. Description of the Background Art
A. Background Art
(A-1) Basic Structure of Level Converter Circuit
FIG. 15 is a block diagram of an exemplary LSI which accomplishes ECL input and output. Power is supplied from two power supplies GND (=0 V) and V.sub.EE (&lt;0 V), and an input buffer 1, an internal gate 2, and an output buffer circuit 3 are driven. Application of the BiCMOS technique to these components is disclosed in NEC Technical Journal Vol. 43, No. 12, 1990, pp. 119-121.
FIG. 16 is a circuit diagram of the output buffer circuit 3 of FIG. 15. The output buffer circuit 3 comprises a level shifter G.sub.20 and a current switch G.sub.30. Such a construction is disclosed in, for example, Japanese Patent Application Laid-Open No. 63-313916 (1988). The output buffer circuit 3 has the function of converting a CMOS level signal outputted from the internal gate 2 into an ECL level signal.
A signal CI at the CMOS level is applied to an input terminal. For instance, when the input signal CI is "H" at the CMOS level, a PMOS transistor P.sub.1 is off. Then current fed from a current source S.sub.1 flows through a resistor R.sub.3 connected in parallel with the PMOS transistor P.sub.1. Thus, the base potential of an NPN transistor Q.sub.10 is lower than the GND by a constant voltage. A potential lower than the base potential of the NPN transistor Q.sub.10 by the base-emitter voltage of the transistor Q.sub.10 is applied to the base of an NPN transistor Q.sub.1 serving as an input of the current switch G.sub.30, and the potential is "L" at the ECL level. Consequently, current fed by an NPN transistor Q.sub.2 increases and a voltage drop in a resistor R.sub.2 connected to the collector of the transistor Q.sub.2 increases. This reduces the base potential of an NPN transistor Q.sub.0 for output, and an output signal EO becomes "L" at the ECL level.
On the other hand, when the input signal CI is "L" at the CMOS level, the transistor P.sub.1 is on. Current supplied from the current source S.sub.1 flows through the transistor P.sub.1, and the base potential of the transistor Q.sub.10 becomes substantially equal to the potential GND (also designating the power supply) of the power supply GND. Then "H" at the ECL level is applied to the base of the transistor Q.sub.1 through an emitter-follower circuit comprised of the transistor Q.sub.10 and a current source S.sub.2, and the output signal EO becomes "H" at the ECL level.
The construction of the current switch G.sub.30 is disadvantageous in that large current is to be fed from the current source S.sub.3 connected commonly to the emitters of the transistors Q.sub.1 and Q.sub.2, resulting in a large amount of power consumption. This disadvantage will be discussed with the description of operation of the circuit of FIG. 16.
In general, an output buffer circuit for outputting the ECL level has an output terminal connected to a terminating power supply V.sub.TT (also designating the voltage) through a terminating resistor R.sub.E. It is a common practice to select a 50.OMEGA. terminating resistor R.sub.E and a -2 V terminating voltage V.sub.TT. Potentials V.sub.OH and V.sub.OL corresponding to "H" and "L" at the ECL level are set to about -0.9 V and about -1.7 V, respectively. A reference potential V.sub.BB is set to about -1.3 V which is intermediate the potentials V.sub.OH and V.sub.OL.
FIG. 17 is a circuit diagram of an equivalent circuit including the output transistor Q.sub.0 and adjacent components when "H" is applied to the base of the transistor Q.sub.1 and the transistor Q.sub.1 turns on while the transistor Q.sub.2 turns off. Current I.sub.OH flowing through the output transistor Q.sub.0 is expressed as: ##EQU1##
Since the transistor Q.sub.2 is off, current fed from the current source S.sub.3 does not flow through the resistor R.sub.2 connected to the base of the transistor Q.sub.0, but only a base current I.sub.BH of the transistor Q.sub.0 flows therethrough. The potential V.sub.OH is EQU V.sub.OH =0-I.sub.BH .multidot.R.sub.2 -V.sub.BE ( 2)
where V.sub.BE is a base-emitter voltage of the output transistor Q.sub.0. Further, ##EQU2## where H.sub.FE is a direct current amplification factor of the transistor Q.sub.0. From Equations (1) and (3) is given ##EQU3## Equation (4) is arranged into ##EQU4## From FIG. 5 is found that the potential V.sub.OH rises toward -V.sub.BE (=-0.85 V) as the resistance of the resistor R.sub.2 decreases and the potential V.sub.OH drops toward the potential V.sub.TT (=-2.0 V) as the resistance of the resistor R.sub.2 increases. To set the potential V.sub.OH to about -0.9 V, a smaller resistance of the resistor R.sub.2 is desirable.
FIG. 18 is a circuit diagram of an equivalent circuit including the output transistor Q.sub.0 and adjacent components when "L" is applied to the base of the transistor Q.sub.1 and the transistor Q.sub.1 turns off while the transistor Q.sub.2 turns on. Current I.sub.OL flowing through the output transistor Q.sub.0 is expressed as: ##EQU5##
Since the transistor Q.sub.2 is on, current I.sub.S fed from the current source S.sub.3 as well as a base current I.sub.BL of the transistor Q.sub.0 flows through the resistor R.sub.2 connected to the base of the transistor Q.sub.0. The potential V.sub.OL is EQU V.sub.OL =0 -(I.sub.BL +I.sub.S).multidot.R.sub.2 -V.sub.BE( 7)
Similar to Equation (3), ##EQU6## From Equations (6) and (8) is given ##EQU7## Equation (9) is arranged into ##EQU8## From Equation (5) is found that a smaller resistance of the resistor R.sub.2 is desirable. To set the potential V.sub.OL low (to -1.7 V), it is necessary to increase the current I.sub.S.
As above described, large current I.sub.S is required to set the potential V.sub.OH high and the potential V.sub.OL low for achievement of ECL level specifications, resulting in a large amount of power consumption.
(A-2) Reduction in Operating Power
To solve the problem discussed in the previous section (A-1), the technique of varying the resistance of the resistor R.sub.2 in response to on/off of the transistors Q.sub.1 and Q.sub.2 has been devised.
FIG. 19 is a circuit diagram of a current switch G.sub.301 which is an example of the technique. Such a technique is disclosed in Japanese Patent Application Laid-Open No. 3-259617 (1991).
The current switch G.sub.301 is constructed such that a PMOS transistor P.sub.3 is connected in parallel with the resistor R.sub.2 in the current switch G.sub.30 of FIG. 16 and has a gate connected to the collector of the transistor Q.sub.1.
The transistor P.sub.3 turns off when "L" is applied to the base of the transistor Q.sub.1 and the transistor Q.sub.1 turns off whereas the transistor Q.sub.2 turns on. The current switch G.sub.301 is similar in operation to the current switch G.sub.30.
The transistor P.sub.3 turns on when "H" is applied to the base of the transistor Q.sub.1 and the transistor Q.sub.1 turns on whereas the transistor Q.sub.2 turns off. Hence, the resistance of a resistor between the base of the output transistor Q.sub.0 and the power supply GND in the current switch G.sub.301 is lower than that in the current switch G.sub.30. This means that the resistance R.sub.2 in Equation (5) is substantially lower. Thus, the potential V.sub.OH to be calculated from Equation (5) can be high if the resistance R.sub.2 is set high so that the potential V.sub.OH to be calculated from Equation (10) is lowered with the small current I.sub.S. That is, the power consumption based on the current I.sub.S is suppressed.
In the current switch G.sub.301, the on/off state of the transistor P.sub.3 is controlled by differences in voltage drop in the resistor R.sub.1 generated with on/off of the transistor Q.sub.1. This presents the problem of low-speed operation left unsolved.